1. Field of the Invention
This invention relates to the field of integrated circuits. More particularly, this invention relates to modifying the layout of an integrated circuit after it has initially been formed in order to, for example, fix bugs or performance difficulties which have only become apparent after the layout was initially formed.
The set up costs for manufacturing an integrated circuit are high. As integrated circuits increase in complexity and density, the masks and other materials necessary to manufacture those integrated circuits also increase in cost. Accordingly, if when an integrated circuit has been manufactured and is tested it is determined that there is a problem with its design, such as a bug, performance limitation or missing piece of functionality, then it is disadvantageously expensive to remake all of the masks and other materials necessary to manufacture the integrated circuit in order to fix the problem.
2. Description of the Prior Art
One known way of dealing with this issue is to provide within the integrated circuit what are termed “spare gates” which are positioned throughout the integrated circuit and which may be connected via a suitable modification to the routing layers in order to replace functionality which is flawed elsewhere or provided new functionality that may be necessary. A problem with this approach is that such spare gates tend to be disadvantageously large and are often not located close to the portion of the integrated circuit in which the problem has arisen. This results in long signal routing paths being necessary, which itself presents a performance limitation. Furthermore, with the increasing complexity of integrated circuits the ability to achieve such routing becomes increasingly difficult as many layers of the integrated circuit may need to be traversed. The spare gates even though large are sometimes inadequate to provide the functionality required to fix a problem.
Another approach which has been used recognises that when the standard cells forming an integrated circuit have been placed into position, typically by the automated synthesis tools, there exist many unused sites between the standard cells. These unused sites may be filled with simple fill cells (e.g. that provide additional decoupling capacitance). Another possibility is to fill these unused sites with programmable cells which are not at first instance used but which have the capability to be brought into use and connected to standard cells or other portions of the integrated circuit by modifying only a relatively few layers within the integrated circuit. Thus, the changes in the masks necessary to use these programmable cells, i.e. turn them into programmed cells, can be limited to only a small number of the total number of masks and accordingly the cost of making such a change may be reduced. As an example, a programmable cell may include the diffusion layers and gate layers necessary to provide transistors for use in forming logical elements, but may not include any metal layers for connecting up and rendering those gates operational or configuring them to provide a particular logical function. The programming of such programmable cells may be to provide an appropriate metal layer over the underlying diffusion and gate layers to connect up the gates in a desired manner. Such programming of the programmable cells yields programmed cells and may involve the modification of only one metal layer (and/or the contact layer) within the plurality of layers which make up the integrated circuit, each of these layers having an associated mask. In practice it may also be necessary to add routing connections in other layers in order to connect the programmed cells up to other points within the integrated circuit. Nevertheless, the number of masks needing to be modified can be reduced compared to producing a complete new design to solve a problem.
In order to obtain good use of this technique it is important that there are sufficient programmable cells in the locality of the bug which occurs or the locality where the additional functionality is required. If insufficient programmable cells are available, then it may not be possible to fix the bug or the fix may be inefficient due to excessive routing delays. Accordingly, it is advantageous to provide a large number of programmable cells into the spaces which are not used by the standard cells.
One approach to providing programmable cells within the design is to place the standard cells as required using the normal synthesis, place and route tools and then search through the layout to identify any placement sites large enough to accommodate a programmable cell and place a programmable cell at each of these sites. Remaining empty sites can be filled with standard fill cells. In use, the designer wishing to convert a position within the integrated circuit currently occupied by a programmable cell into a programmed cell for fixing a problem must manually identify a suitable programmable cell located near the problem to be solved, manually remove that programmable cell from the layout, fill the now empty space with a suitably selected programmed cell (e.g. selected from a library of programmed cells having appropriate metal layers to achieve the desired functionality) and then can automatically generate routing to connect that programmed cell to the desired point or points within the remainder of the integrated circuit. A problem with this approach is that there is considerable scope for further errors to be introduced in the placement choices made by the designer seeking to fix an existing problem.
Another technique is to predefine an array of programmable fill sites overlying the array of standard cell placement sites. When the layout is being formed, the standard cells are placed at appropriate standard cell sites. A search may then be conducted for programmable fill sites which are completely unoccupied by any standard cells or portions of standard cells. Programmable cells are then placed in identified empty programmable fill sites. These programmable cells will have known locations associated with the predefined grid of programmable fill sites. Remaining unused standard cell sites which are not occupied by a standard cell or by a programmable cell are then filled with fill cells.
When it is desired to use some of the programmable cells to address a problem, automated mechanisms may be used by first deleting all of the programmable cells from the layout. These deleted programmable cells will have known locations associated with the programmable fill site grid. The programmed cells needed address the bug can then be identified. Since the empty sites where placement of these program cells is possible are known from the programmable fill site grid, the standard placement algorithms (or slightly modified forms thereof) can be used to automatically place the programmed cells in positions suitable for connection and use with the other portions of the integrated circuit with which it is desired they interact. The automated routing mechanisms may then be used to provide signal routing to those program cells. This capability to provide automated placement and routing using empty sites corresponding to previously placed programmable cells reduces the likelihood of error in the use of the programmed cells to fix a problem which has been identified.
A disadvantage associated with this second approach is that since the programmable fill site grid is predefined and a programmable cell is not placed unless a programmable fill site is completely empty, it tends to provide fewer programmable cells within the initial layout. Thus, fewer programmable cells are available to fix problems which have been identified. Furthermore, the maximum size of blocks of programmable cells tends to be smaller limiting the functionality that can be provided at one location. This reduces the capability of these mechanisms to solve problems which have been identified.